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Allwinner /D1H /SMHC[2] /SMHC_IDIE

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Interpret as SMHC_IDIE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TX_INT_ENB)TX_INT_ENB 0 (RX_INT_ENB)RX_INT_ENB 0 (FERR_INT_ENB)FERR_INT_ENB 0 (DES_UNAVL_INT_ENB)DES_UNAVL_INT_ENB 0 (ERR_SUM_INT_ENB)ERR_SUM_INT_ENB

Description

IDMAC Interrupt Enable Register

Fields

TX_INT_ENB

Transmit Interrupt Enable
RX_INT_ENB

Receive Interrupt Enables
FERR_INT_ENB

Fatal Bus Error Enable
DES_UNAVL_INT_ENB

Descriptor Unavailable Interrupt
ERR_SUM_INT_ENB

Card Error Summary Interrupt Enable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data